First Intel Z990 Specs Leak Online — Chipset Gets More Powerful and More Power-Hungry

The tech insider community has obtained the first batch of measurable specs for Intel’s future flagship Z990 chipset. The chipset is designed for motherboards using the LGA 1954 socket, which will serve as the foundation for the Nova Lake-S platform. The photo isn’t exactly high-res, but it still allows us to compare the new chip to the current-gen Z890 chipset.

Based on the numbers we’re seeing, Intel’s engineers reworked the die layout. The Z990 package measures 25 × 24 mm, while the Z890 comes in at 28 × 23.5 mm. Meanwhile, the exposed die area has shrunk from 92.9 mm² to roughly 72.5 mm² — nearly 22% smaller than its predecessor. Reducing die size while also tweaking the package proportions suggests a move to a more mature or optimized version of the manufacturing process.

According to the same sources, the Z990’s typical power draw comes in at 7.9W. For comparison, the current Z890 has an official typical TDP of 6W. Peak power consumption on the new chipset hits 14W — noticeably higher than the 10W we’re used to seeing from its predecessor. Meanwhile, details have surfaced on the more affordable Z970 chipset, which will run on the same platform. Its baseline figure is capped at 6.4W, putting it close to the power draw of current 800-series solutions.

The reason for such a wide power gap within the 900-series family comes down to interface configuration. Early unofficial reports claimed that Intel plans to strictly segment chipset features. Only the flagship Z990, along with enterprise variants Q970 and W980, will get PCIe 5.0 lanes straight from the chipset. The Z970 model will lack that capability and will rely solely on Gen5 lanes provided by the CPU. And it’s exactly this feature cut that keeps its thermal envelope more modest.

The Z990’s peak power jump to 14W explains why motherboard makers are getting ready to bring back chunky heatsinks on the hub. At Computex not long ago, GIGABYTE teased an AORUS Z990 PRO board with serious chipset cooling — and it’s now clear that this isn’t just a design flex, but a technical necessity. Keep in mind, all of these specs are based on unconfirmed info and a single low-quality photo.

Do you think the nearly twofold increase in chipset peak power draw is justified for extra PCIe 5.0 lanes from the hub itself, or should board makers just stick to CPU-provided high-speed lanes? Drop your take in the comments.